1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to a phase locked loop system having a controllable variable delay circuit for controlling a delay of a VCO output signal based on an initial phase difference.
2. Description of Related Art
Storage devices, such as hard disk drives (HDD), magnetot-optical disks (MO) and digital video disks (DVD), have been developed as data storage devices for image data and audio data, and recently their memory capacities and speeds have been increased.
In order to reproduce (read) data from these storage media, a sync clock must be extracted in advance from bit sync detection data on a disk, and a clock of a reproduction circuit must be synchronized with this sync clock. In short, so-called "bit synchronization" must be achieved. Generally, a phase locked loop (PLL) circuit is used to achieve the bit synchronization.
To reproduce data on the HDD, first a bit sync pattern is read from the head part in an area where user data are stored. A reproduction circuit (a read channel) is controlled so that this circuit may sample the bit sync pattern waveform at a specific time, which is determined in advance, in the bit sync pattern. In short, the PLL circuit uses a feedback controller to control the phase and the frequency of a clock so that the read channel performs sampling of the bit sync pattern signal at an appropriate time.
FIG. 1 illustrates a conventional PLL circuit 100. In response to a read gate signal 5, an error correction logic to circuit (ECL) 1 compares a value of a sampled read-back signal 6, which is sampled using a clock output by a voltage controlled oscillator (VCO) 2, with a sampling point (target value) that is determined in advance. The ECL 1 identifies a phase difference between the output clock of the VCO 2 and a target clock (a clock used to reproduce an appropriate read-back signal).
The ECL 1 feeds a determined phase difference signal back to a current digital to analog converter (DAC) 3. The current output from the current DAC 3, which varies in accordance with the fed back phase difference signal, flows into a loop filter circuit 4 connected to the input terminal of the voltage controlled oscillator 2. The oscillation frequency and the phase of the voltage controlled oscillator 2 are controlled in accordance with a voltage applied to the loop filter circuit 4. While the feedback control sequence is repeated, the "clock output" by the VCO 2 can be synchronized with the "target clock," which samples the read-back signal 6 at appropriate times. So-called bit synchronization is thus achieved.
In the conventional PLL circuit 100 in FIG. 1, the read gate signal 5 is transmitted to the ECL 1 asynchronously with the sampled read-back signal 6. Therefore, the initial phase difference between the output clock of the VCO 2 and the target clock is .+-..pi. at the maximum. The PLL circuit 100 initiates the operation in accordance with the time at which the read gate signal 5 becomes active, in order to reduce the initial phase difference to zero. At this time, how fast the initial phase difference is reduced to zero is important for the early achievement of the bit synchronization.
With the conventional PLL circuit 100, however, for the following reasons, reducing the initial phase difference to zero can require a relatively long period of time. As is described above, the oscillation frequency and the phase of the VCO 2 are controlled using a terminal voltage, which is changed in accordance with the strength of a control current that flows in the loop filter circuit 4 connected to the input terminal of the VCO 2. In other words, the oscillation frequency and the phase of the VCO 2 are controlled with an analog process. Thus, the frequency and the phase of the clock cannot be controlled independently. Even when the frequency of the clock is near the frequency of the target signal, if the strength of the control current is changed to adjust the phase of the clock, the frequency is changed accordingly, and is shifted away from that of the target signal.
FIG. 2 illustrates the time lag of zero cross timings of a frequency error and a phase error in the conventional PLL circuit of FIG. 1. In FIG. 2, as is indicated by the broken lines, sampling is performed for the bit sync pattern at the leading edge of a clock pulse. At the first portion of the clock, the frequency of the PLL clock substantially matches the frequency of a target clock. However, the phase of the PLL clock is delayed relative to that of the target clock. And, the PLL, therefore, advances the phase.
As a result, the leading edge of the PLL clock gradually approaches the leading edge of the target clock (A in FIG. 2). However, since the frequency is also advanced, the next leading edge of the PLL clock advances too far, beyond the leading edge of the target clock (B in FIG. 2). At this time, the PLL delays this advance.
As this control sequence is repeated, the frequency and the phase of the PLL clock match those of the target clock; however, as is shown in FIG. 3, an extended period of time is required for the frequency and the phase to converge on the target. In particular, the convergence is extended when there is a large initial phase difference between the PLL clock and the target clock. In other words, the larger the initial phase difference is, the more time the bit synchronization requires.